Chips & Supply · United States

Huawei tells customers to find their own AI chip memory, effectively outsourcing procurement to the black market

Credited to The Decoder · the-decoder.com · 10h ago

Photograph · The Decoder

Huawei can't get enough memory for its AI chips, pushing customers onto the black market. A sophisticated smuggling network has sprung up to fill the gap, exploiting a loophole in U.S. export rules.

Huawei is telling some customers to source the memory for its AI chips themselves, effectively pushing buyers onto the black market, The Information reports. The company plans to launch the Ascend 960DT early next year, which it says will double the performance of its current chips. But Huawei's Chinese suppliers can't produce enough High-Bandwidth Memory (HBM), and U.S. export rules block direct purchases from Samsung and SK Hynix. Together, those two companies control over 80 percent of the global market.

Smugglers have found a workaround. They bundle HBM with cheap server processors whose performance falls below the export threshold, then ship the packages to China through Hong Kong. Once there, workshops separate the memory chips from the processors. The process is fragile and the error rate is high, but the margins make it worth it. Ad

Smuggled memory prices have surged to $4,000 per unit

Prices for smuggled HBM3E memory have jumped from a few hundred dollars to around $4,000 per unit in just one year, according to a broker in Shenzhen. Each AI chip needs six to eight units, meaning the memory alone can cost up to $32,000. Ad

The black market doesn't run on smuggling alone. Older Nvidia GPUs stripped for parts and excess inventory from chip designers who scrapped projects or cut orders also feed the supply. South Korea's customs authority had uncovered trade violations worth $560 million by May, already surpassing the previous full-year record. A third of that total involved strategic goods like chips exported without proper authorization or with false declarations.

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Chips & SupplyUnited States

Same fab, different paths: Kioxia and Sandisk diverge on HBF

Credited to Blocks & Files · blocksandfiles.com7h ago

Useful

NAND fab joint-venture (JV) partners Kioxia and Sandisk have differing views on the SK Hynix-led High-Bandwidth Flash (HBF) initiative, with Sandisk supporting it and Kioxia so far neutral and staking out an alternative architectural position.

Similar in concept to High-Bandwidth Memory (HBM), the HBF concept involves multiple layers of NAND with connecting wires (Through-Silicon Vias or TSVs) linking each layer to a base interposer logic and then unit, which connects them to a host GPU in parallel, not serially.

The HBF multi-die stacking step is done at the die level after the dies have been cut out from a wafer which is built using 3D-NAND, which is itself layered. Known-good dies are vertically stacked (typically 8-high or 16-high configurations in the first HBF spec) and interconnected with TSVs and microbumps. That means they have to have been fabricated with a design that facilitates TSV and microbump addition.

As we understand it, standard NAND dies (and the wafers that produce them) generally cannot be used as-is for HBF. The NAND dies in the HBF stack must be specifically designed and fabricated to enable TSVs and microbump connectivity. This is because:

TSV placement and area: TSVs must pass vertically through the dies. This requires reserved keep-out zones in the die layout, additional process steps (via etching, filling, etc.), and extra die area. A standard 3D NAND die designed for conventional SSD packaging has no such structures or space allocated.

Stacking requirements: Lower dies in the stack need TSVs that connect through them to the base logic die and interposer. Standard dies lack these pathways.

Internal architecture differences: HBF dies are typically optimized for much higher internal parallelism (many more independent planes/sub-arrays) to achieve the target bandwidth via concurrent reads.

What we are getting at here is that, because Sandisk owns no independent wafer fabs, currently Sandisk’s only access to a fab is through its JV with Kioxia. It would thus potentially need to access a fab that produces HBF NAND wafers. We don’t see this JV producing HBF NAND wafers just for Sandisk.

Sandisk and SK Hynix launched the HBF Spec Standardization Consortium and a dedicated workstream under the Open Compute Project (OCP) in February 2026. They are the main contributors to the first open technical specification, which covers NAND die stacks (8-high/16-high, up to 512 GB), bandwidth grades (~0.4–3.0 TB/s), UCIe interconnect, packaging, reliability, and software guidance. The spec was released via OCP in early August 2026.

Google and Tenstorrent then joined as consortium members.

HBF evangelist, Professor Kim Jung-ho of the School of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) said in January “Samsung Electronics and Sandisk plan to integrate HBF into products from Nvidia, AMD, and Google by late next year or early 2028.”

In October Sandisk said: “HBF reached a milestone in FQ1 with tape-out of our first HBF memory die; samples of our first HBF-based products remain on track for next calendar year.”

Meanwhile, Kioxia has not joined the HBF consortium. Its own architectural vision flash and SSD developments include:

GP Series, Optane-class, SSD using gen 3 XL-FLASH with >20 million IOPS 512-byte random read performance.

Liquid-cooled NX1 Series E1.S NVMe SSDs for data centers and liquid-cooled version of its PCIe gen 5 CM9 datacenter SSD.

Plans to use fast NAND as a DRAM alternative, according to Japan’s Nikkei outlet. It intends to use a CXL (Compute Express Link) module wth memory-access speed across a PCIe link. Combining high-speed NAND with a CXL controller module reduces data-read latency to less than one-tenth that of conventional NAND products.

A prototype, large-capacity, high-bandwidth flash memory module with 5 TB capacity and 64 GB/s bandwidth in August 2025 for edge servers, not data center GPU servers. Its configuration has daisy-chained connections with so-called beads of flash memory, not stacked layers, plus high-speed transceiver technology enabling bandwidth of 128 gigabits per second (Gbps), along with techniques to enhance flash memory performance. It utilises differential serial signalling, not parallel signalling like the SK Hynix and Sandisk HBF.

There is then, a difference between Kioxia and Sandisk around HBF technology, with Kioxia considering serial connectivity without layer stacking, and Sandisk/SK Hynix favoring layer stacking with parallel TSV connectivity.

SK Group Chairman Chey Tae-won suggested in September that an SK Hynix partnership with Kioxia could be interesting.

As background, SK Hynix is a Kioxia investor through holding convertible bonds that could be converted into a 14.19 percent share holding with voting rights. This would be the largest single voting share holding. Kioxia also uses SK Hynix DRAM in some of its SSDs.

Kioxia CEO Hiroo Ota opposed the idea, telling The Japan Times: “We can’t just say, ‘Well then, let’s make it three companies,’” … We have no idea what prompted (Chey) to say what he did.” The spectacle of South Korea’s SK Group chairman and Japan’s Kioxia CEO disagreeing like this in public is surprising as such differences of opinion at this level are usually kept private.

If the Kioxia-Sandisk JV has no plans to manufacture SK Hynix-Sandisk style HBF NAND wafers then where would Sandisk get its source HBF wafers?

A TrendForce April 2026 document said: "According to ETNews, sources say the company has begun engaging materials, components, and equipment partners to build out an ecosystem for an HBF prototype production line. It aims to introduce prototypes in the second half of this year, with Japan emerging as a leading candidate for the production site. The industry expects the pilot production line to be completed in the second half and begin operation around year-end, with commercialization targeted for 2027."

This indicates that Sandisk could potentially be thinking about owning and operating its own NAND fab for HBF NAND, separate from its Kioxia JV. That would add tension to its partnership with Kioxia.

We have asked Sandisk about the existence of a separate HBF fab idea.

Original · Blocks & Files

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Chips & Supply · United States

AI Hardware’s Hidden Cost: Between Orders and Output

Credited to EE Times · eetimes.com · 7h ago

Photograph · EE Times

Alphabet’s TPU inventory, Intel’s manufacturing tradeoffs, and equipment suppliers’ balance sheets show how capital builds up along the path to usable AI computing capacity.

Alphabet’s inventory rose from $2.4 billion at the end of 2025 to $13.3 billion in September 2026, reflecting in part Google’s expanding role as an AI hardware supplier.

Google now sells complete Tensor Processing Unit (TPU) systems for deployment in customer facilities, alongside the computing capacity it provides through Google Cloud. Selling hardware brings a different set of working capital demands.

During Alphabet’s third-quarter earnings call, CFO Anat Ashkenazi described the process: Customers sign contracts, orders enter backlog, and Google begins building the systems ahead of delivery and billing. Google Cloud CEO Thomas Kurian confirmed that components are procured after contracts are signed.

The contracts provide demand visibility. Alphabet, however, does not disclose how much of its inventory consists of TPU systems or how quickly those systems will be delivered.

That leaves an increasingly relevant measure of the AI buildout: the time between committing capital and putting hardware to work.

Intel’s manufacturing tradeoffs

Intel’s third-quarter disclosures show how difficult that conversion can become.

CFO David Zinsner confirmed that manufacturing capacity in Oregon originally planned for Intel 18A-based Panther Lake processors is being redirected toward Intel 3 to support demand for Granite Rapids server CPUs.

The additional Intel 3 capacity is expected in the second half of 2027. Intel continues to develop and manufacture products on 18A, but the reallocation shows how changes in demand can force manufacturers to revisit capacity plans across process generations.

Increasing wafer output is only part of Intel’s challenge.

CEO Lip-Bu Tan also identified shortages of advanced organic substrates used in EMIB packaging as a constraint on scaling production. The company is working to improve yields and cycle times while securing additional substrate supply.

Following the quarter, Intel entered two agreements to secure future substrates, with estimated funding requirements of $5.3 billion to $6.1 billion. Approximately $3.3 billion is expected through the end of 2027, although some contractual terms remained unfinished.

The wafer capacity decision and EMIB substrate constraints affect different parts of Intel’s manufacturing operations. Both illustrate how production plans depend on capacity beyond the fabrication process itself.

Meanwhile, Intel recorded higher inventory-related charges in its client computing business as it adjusted product mix to demand.

Server products faced supply constraints while other products generated inventory charges. The aggregate inventory balance reveals little about which components can be turned into shipments.

A fabricated die still requires packaging and testing. Substrates are engineered for specific electrical, thermal, and mechanical requirements. Components intended for one processor cannot necessarily be redirected to another.

AI accelerators face similar dependencies. TSMC’s CoWoS packaging technology and high-bandwidth memory integration add manufacturing stages that must scale alongside wafer production.

More wafer starts do not automatically produce more shippable processors.

Inventory moves upstream

Lam Research ended September with $4.55 billion in inventory, up from $4.28 billion in June. Nearly the entire increase came from raw materials. Work in process declined slightly, while finished goods remained largely unchanged.

KLA’s inventory increased from $3.65 billion to $4.09 billion over the same period, with increases in raw materials and work in process.

The composition matters. Components and partially assembled equipment absorb capital before completed systems can be delivered. Their accumulation may reflect production plans, supplier lead times, or changes in customer requirements.

Neither company’s figures establish that finished machines are stranded by shortages.

Semiconductor manufacturing equipment contains highly specialized components that must meet demanding optical, mechanical, electrical, and process specifications. Suppliers may need to secure those components well before a machine reaches the customer.

Changes in delivery schedules can therefore affect working capital long before they appear in revenue.

More output from installed equipment

ASML reported €3.29 billion in third quarter installed-base management sales, above guidance, partly driven by demand for productivity upgrades. The figure also includes services and other activities.

For chipmakers, improving the throughput of equipment already installed can provide capacity without waiting for another machine to be manufactured, delivered, and qualified.

But a faster lithography system increases completed wafer output only when the rest of the production line can accommodate it.

Deposition, etch, metrology, and inspection capacity must keep pace. Yield losses and downtime can erase gains in nominal equipment speed.

The economics of an upgrade depend on whether it addresses the operation limiting production. A relatively modest improvement at that point can be more useful than additional capacity elsewhere in the fab.

From packaging to power

The same dependencies continue beyond semiconductor manufacturing.

AI accelerators must be integrated with memory, networking, power delivery, and cooling. Completed systems then need data centers capable of operating them.

Grid connections, transformers, substations, and cooling infrastructure follow development schedules that can differ substantially from semiconductor production cycles.

A system may be ready for installation before the facility intended to operate it is ready to receive it.

Alphabet’s September filing shows the scale of the associated commitments. The company disclosed $924.4 billion in future purchase commitments covering technical infrastructure, inventory, energy, content, and other requirements. It also reported $130.5 billion in future payments for leases that had not commenced, primarily associated with data center and energy infrastructure.

These are different contractual arrangements, including commitments unrelated to AI. They are neither a single capital expenditure forecast nor amounts already spent.

They do, however, illustrate how far ahead companies must plan and commit resources.

A processor generation can change while the buildings, electrical systems, and supply agreements intended to support computing demand remain in place. Compatibility and flexibility become important when assets have such different useful lives.

The timing has financial consequences as well. Hardware suppliers commit working capital before delivery, while cloud operators and AI developers make long-term commitments to future computing capacity.

Signed contracts may improve revenue visibility, but they cannot shorten equipment qualification, grid connections, or facility commissioning.

The longer the interval between capital commitment and productive use, the greater the pressure on working capital and investment returns.

Follow the conversion

The next earnings reports should help establish how quickly the industry’s commitments are becoming productive assets.

At Alphabet, the measures are TPU system deliveries, inventory conversion, and operating cash flow.

At Intel, the test is whether additional Intel 3 capacity translates into server shipments, alongside progress on substrate availability and manufacturing yields.

For Lam and KLA, inventory composition should be assessed against equipment deliveries, customer commitments, and inventory provisions.

At fabs, installed equipment must translate into qualified capacity and completed wafers. For data center operators, the corresponding measures include facility commissioning and utilization of installed computing systems.

A wafer can be finished while its package remains unavailable. A machine can be installed without increasing fab output. A completed AI system can wait for power.

The capital has already been committed at each stage. The financial return depends on when the entire system can operate.

Disclosure: The author previously held finance and operations roles at Intel. This analysis is based on publicly available company filings and earnings disclosures.

Intel Foundry Gains Steam, but External Wins Remain Key

Google-Marvell Deal Expands Custom Silicon Past the TPU

RELATED TOPICS: AI HARDWARE, CHIP MANUFACTURING, COMPUTE, SEMICONDUCTORS, WAFER FABS

COMPANIES: ALPHABET, ASML, GOOGLE, INTEL, KLA, LAM

Ron Honig is co-CEO of From Honig Family Office. He previously spent more than two decades in the technology industry, including at Intel, with a long-standing focus on the semiconductor sector. Follow Ron on LinkedIn