Chips & Supply · United States

Accepting Orders for the LED Light-Sourced Projection Aligners

Credited to EE Times · eetimes.com · 3h ago

Photograph · EE Times

The UX-4 series is a full-field projection aligner that has a proven track record over many years as lithography equipment that enhances production efficiency, primarily for power semiconductors, MEMS sensors, and devices related to communication and photoelectronic fusion (optical semiconductors) In recent years, environmental regulations concerning the use and emission of chemical substances have tightened in the semiconductor industry, impacting the entire sector. Against this backdrop, adoption of LED light sources in lithography equipment has been progressing. However, extending exposure times due to insufficient intensity remains a challenge for layers requiring a high exposure dose.

To address this challenge, based on the solid-state light source design technologies cultivated since its founding, Ushio developed an LED light source unit that achieves intensity equivalent to conventional mercury lamps and has successfully developed the UX-44101SCB and UX-45114SCB, incorporating this LED light source unit. As next-generation electronic devices essential to the evolution of IoT, 5G, and mobility drive the demand for larger wafer sizes and higher-precision layers, even processes requiring high exposure dose—such as Bump ※1 and WLP ※2 can achieve high throughput equivalent to conventional mercury lamp equipment.

In addition, compared with conventional mercury lamps, the equipment enables instantaneous turn-on and turn-off during exposure, thereby extending the lifetime of the light source and significantly reducing running costs after installation. As a leading company in full-field projection aligners for wafers, Ushio will continue to contribute to the realization of a convenient and comfortable society through light. ※1 A process to form microscopic bump-shaped metal terminals called “bumps” (such as solder balls) on the electrode parts of semiconductor chips. ※2 A process to perform batch packaging (encapsulation) and terminal formation on the whole wafer before cutting the silicon wafer into square chips.

Main Features

・ Full-field projection exposure: No Mask damage, High productivity of 120 WPH or more ・Deep depth of focus: Exposure to 3D surface shapes, thick-film resist exposure ・Automation compatible: Inline, Online, OHT/AGV ・Mercury-free: Compatible with LED light sources

Specifications

Specifications/Model — UX-44101SCB; UX-45114SCB (Provisional specifications); UX-45114SC (Lamp Light Source)

Supported wafer materials — Si, GaAs, GaN, GaP, InP, SiC, Glass, Sapphire, Ceramics, LN, LT, Thin & Thick

Automation Options — EFEM, Automatic mask handling, SECS/GEM online, AGV, Inline with coater/developer

*Appearance and specifications are subject to change without prior notice.

For further information, please check the website below.

Mask aligner UX-4 Series (Full Field Projection) | Ushio Inc.

Ushio Inc. Photolithography Division Sales and Marketing Department

Please use the online inquiry form on our website.

Chips & SupplyUnited States

Hanmi Semiconductor, Hanwha Semitech Agree to Mediate TC Bonder Patent Dispute

Credited to TheElec · thelec.net1h ago

Useful

A patent dispute between Hanmi Semiconductor and Hanwha Semitech over thermocompression (TC) bonding equipment used to manufacture high-bandwidth memory (HBM) will be put on hold as the companies pursue mediation.

A Hanwha Semitech official said on November 3 that the two companies had agreed to enter mediation proceedings before the Industrial Property Rights Dispute Mediation Committee, following a recommendation from the Intellectual Property Trial and Appeal Board last month.

"We will participate in the mediation process in good faith," the official said. The company declined to disclose details, including the mediation schedule.

A Hanmi Semiconductor official also said the company had followed the court's recommendation in accordance with customary practice.

The Industrial Property Rights Dispute Mediation Committee is a body that seeks to resolve disputes involving patents and other intellectual property rights through agreements between the parties. It operates under the Ministry of Intellectual Property to reduce the time and costs associated with litigation.

During mediation, a panel of experts hears arguments from both sides and seeks to broker a settlement. The process can address multiple types of disputes, including civil and criminal litigation and patent proceedings. Unless exceptional circumstances arise, mediation is generally completed within three months of an application. Proceedings are confidential.

A successful mediation carries the same legal effect as a court settlement. If mediation fails, the parties can resume litigation.

Hanmi Semiconductor and Hanwha Semitech had originally been scheduled to attend their fourth hearing at the Seoul Central District Court in Seocho, Seoul, on November 3. The hearing was postponed after Hanwha Semitech, the plaintiff, filed a request to change the hearing date the previous day. The companies plan to resume the trial after mediation.

The patent dispute began in December 2024, when Hanmi Semiconductor filed a lawsuit against Hanwha Semitech alleging infringement of its TC bonder patents. Hanwha Semitech subsequently filed a countersuit, claiming that Hanmi Semiconductor's Griffin and Dragon TC bonders infringed its patents and seeking measures including the disposal of the equipment.

Hanwha Semitech alleges that Hanmi Semiconductor infringed three of its patents covering flux application inspection technology, blue-light inspection methods and flux planarization technology. Flux is a material used in the semiconductor chip bonding process. TC bonders are critical equipment for HBM manufacturing, stacking and bonding DRAM dies vertically.

Hanmi Semiconductor has rejected Hanwha Semitech's allegations in their entirety. It maintains that the companies use different light-source wavelengths and defect-detection methods for flux inspection, and that their planarization technologies also differ.

Original · TheElec

Front

Chips & Supply · United States

Five Things You Didn’t Know About Co-Packaged Optics

Credited to EE Times · eetimes.com · 5h ago

Photograph · EE Times

Why advanced packaging will determine whether CPO can scale for the AI era

Co-packaged optics technology is often described as a photonics breakthrough. But its commercial success will depend just as much on advanced packaging: how optical and electronic components are integrated, connected, protected, and manufactured repeatedly at scale.

Artificial intelligence is driving unprecedented demand for computing power and data movement. As processors become more powerful, the electrical connections that move data between them are becoming a growing constraint. They consume power, create heat and can limit how quickly information moves through an AI system.

Co-packaged optics (CPO) offers a new approach. It brings optical engines much closer to the processors and switches they serve, shortening the high-speed electrical path between the processor or switch and the optical engine, so data can transition to optical transmission closer to the source. The goal is higher bandwidth, lower interconnect energy per bit, and lower latency.

But a key point about CPO is often overlooked: advanced packaging decisions determine whether silicon photonics can be integrated tightly enough with electronics to work reliably in real-world systems. Here’s why:

1. CPO is really a heterogeneous integration challenge

A CPO system must combine components that were historically designed, manufactured and packaged separately. Photonic integrated circuits, electronic chips, interconnects, fibers and supporting structures must operate as one tightly integrated system.

That makes heterogeneous integration central to CPO. Advanced packaging provides the architecture for placing dissimilar components close together while preserving electrical performance, optical alignment and thermal stability. The closer these components are integrated, the shorter the electrical distance data needs to travel before it becomes an optical signal.

This is why the package cannot be treated as a container added after the chips are finished. Packaging choices shape the system from the beginning. They influence component placement, signal paths, power delivery, heat management, testability and ultimately the manufacturability of the final product.

Key takeaway: CPO performance depends on how well multiple technologies function together inside the package, not simply on the performance of any single chip.

2. Advanced packaging turns the promise of CPO into a manufacturable system

CPO architectures can deliver impressive performance on paper. The harder task is reproducing that performance across large numbers of devices with the consistency, yield and reliability required for data center deployment.

Advanced packaging technologies such as fan-out wafer-level packaging, hybrid bonding and 3D stacking create different paths for integrating optical and electronic components. Fan-out approaches can expand the available area for dense interconnects. Hybrid bonding and 3D stacking can bring components even closer together, supporting shorter connections and higher bandwidth density.

Each approach creates its own manufacturing requirements. Interconnects must remain uniform across the wafer. Bonded surfaces must be clean and precisely prepared. Thin and sometimes warped wafers must be handled without damage. Small variations can affect electrical paths, optical alignment and overall yield.

Despite the challenges, analysis by Yole Group shows that large-scale CPO deployments in data centers are expected in 2028 to 2030.

Key takeaway: The winning CPO architectures will be the ones that can move from a successful demonstration to a stable, repeatable and productive manufacturing flow.

3. The spaces between components matter as much as the components themselves

In some 3D stacked and high-density CPO integration schemes, when optical and electronic dies are placed or stacked close together, small gaps remain between them. Those gaps may sound insignificant, but they can become critical points of mechanical and thermal stress.

Advanced inter-die gap fill is designed to protect these densely integrated structures. The deposited material must fill deep or irregular spaces without leaving voids. It must remain stable through later processing and thermal cycling, and it must do so without adding excessive stress or wafer distortion.

Lam Research is addressing this challenge with advanced deposition and wafer-handling capabilities designed for thick, void-free dielectric films and high-bow wafers. These capabilities help support the structural integrity and process control needed for complex CPO and 3D integration schemes.

Key takeaway: In advanced packaging, reliability often depends on controlling the tiny spaces, interfaces and material transitions that are invisible in a high-level architecture diagram.

4. Precision must extend across the entire package

CPO requires precision at multiple levels at once. The optical engine must be positioned relative to the electronics and fiber interface. Electrical interconnects must be formed consistently. Fibers must align with optical interfaces. Bonded layers must remain flat and secure. The package must also withstand heat and mechanical stress during manufacturing and operation.

This system-level precision changes the role of semiconductor manufacturing equipment. Deposition, etch, clean, electroplating, bonding preparation, bevel management and process control must work as a coordinated set of capabilities rather than as isolated process steps.

For example, uniform copper features and redistribution layers help create reliable electrical pathways in fan-out packages. Carefully engineered dielectric films and copper surfaces support high-quality hybrid bonding. Wafer shape and edge condition must also be controlled so that downstream steps can maintain alignment and yield.

Key takeaway: CPO scaling will require precision manufacturing across the full package, from the center of the wafer to its edge and from individual materials to the completed integrated structure.

5. Manufacturing collaboration will decide how quickly CPO scales

No single company or technology can solve the CPO manufacturing challenge alone. CPO brings together chip designers, foundries, packaging specialists, equipment providers, materials suppliers, fiber and connector companies, system makers and data center operators.

These participants will need to make architectural and manufacturing decisions together. A packaging choice can affect the optical interface. A bonding approach can affect the thermal budget. A serviceability requirement can influence how fibers and optical engines are attached. Choices made in one part of the ecosystem can ripple through the entire system.

Lam’s role is to help customers translate new CPO and advanced packaging concepts into repeatable processes through a broad portfolio of deposition, etch, clean, electroplating, wafer-handling and process-control technologies. The objective is not only to enable a device to work, but to support the productivity and consistency required for high-volume manufacturing.

Key takeaway: CPO will scale fastest when design, packaging and process development happen together, with manufacturing treated as a foundation rather than a final step.

CPO is emerging because AI infrastructure needs to move more data with greater energy efficiency. Silicon photonics provides the light-based functionality, but advanced packaging is what brings that functionality close to high-performance electronics and turns it into a usable system. According to Yole Group, the photonics packaging market for co-packaged optics may approach $5 billion by 2031, reflecting growing industry investment in integrating optical and electronic components at scale.

The next phase of CPO will therefore be defined not only by better optical devices, but by better integration. Fan-out packaging, hybrid bonding, 3D stacking, inter-die gap fill, precision interconnects and coordinated process control will all play a role in determining performance, yield, reliability and cost.

For the semiconductor industry, the message is clear: CPO will not advance on architecture alone. Its future will depend on the ability to convert innovation across materials, processes and packaging into manufacturing at scale. That is where advanced packaging takes center stage.

Learn more about how Lam is advancing AI with advanced packaging