Chips & Supply · United States

Applied Materials, Intel target AI chip bottlenecks with interconnect scaling and Foveros 3D

Reading from Converge Digest · Credited to DigiTimes $ · digitimes.com · 21h ago

Photograph · DigiTimes

Applied Materials and Intel are expanding their long-running semiconductor R&D relationship with a new collaboration spanning next-generation transistors, interconnects and advanced packaging technologies for AI and high-performance computing. The work will combine capabilities at Applied Materials’ new EPIC Center in Silicon Valley with Intel’s R&D campus in Hillsboro, Oregon, with the goal of shortening the development cycle between new materials and process technologies and their eventual use in high-volume manufacturing.

The collaboration covers both front-end and back-end-of-line semiconductor development. Applied Materials and Intel said their teams are working on new materials, process technologies and device architectures for advanced logic nodes targeting AI workloads, including interconnect scaling as transistor and wiring structures become increasingly complex. The companies did not announce a specific process node, commercial processor, performance target or production schedule associated with the work.

Advanced packaging is another major focus. Applied and Intel plan to develop technologies supporting Intel’s Foveros-based 3D stacking architecture, targeting higher interconnect density, improved power delivery and better thermal performance. These attributes are becoming increasingly important as AI processors integrate more compute, memory and specialized functions into tightly coupled multi-die systems.

R&D Locations — Applied Materials’ EPIC Center in Silicon Valley and Intel’s R&D campus in Hillsboro, Oregon

Logic — New materials, process technologies and device architectures for advanced logic nodes targeting AI workloads

Interconnects — Front-end and back-end-of-line development, including continued interconnect scaling

3D Packaging — Advanced packaging development supporting Intel Foveros-based 3D stacking

System Targets — Higher interconnect density, improved power delivery and enhanced thermal performance

Commercial Timing — No specific process node, product launch or production timetable was disclosed.

“Applied and Intel share decades-long history of deep collaboration focused on pushing the boundaries of materials engineering to advance the semiconductor roadmap,” said Gary Dickerson, President and CEO of Applied Materials. Dickerson said bringing the teams together at EPIC is intended to accelerate transistor, interconnect and packaging innovation for AI computing.

Intel CEO Lip-Bu Tan characterized the collaboration in terms of improving performance, power efficiency and packaging for AI computing, while accelerating the transition from laboratory R&D to high-volume U.S. manufacturing.

🌐 Analysis: EPIC Becomes a Strategic Semiconductor R&D Hub

The Intel collaboration provides another important piece of Applied Materials’ strategy for its new Equipment and Process Innovation and Commercialization — EPIC — Center in Silicon Valley.

Applied originally announced the center in 2023 as a multibillion-dollar R&D initiative intended to change how semiconductor equipment suppliers, chipmakers, universities and other technology partners develop manufacturing technologies. The original plan called for more than 180,000 square feet of cleanroom space and up to $4 billion in incremental capital investment over seven years. As customer projects have developed, Applied now describes EPIC as an approximately $5 billion investment, with capital spending scaling as customer programs commence.

The center is expected to become operationally ready in 2026 and represents what Applied describes as the largest U.S. investment to date in advanced semiconductor equipment and process technology R&D.

The significance is not simply the size of the facility. Applied is attempting to change the semiconductor development model. Traditionally, equipment vendors develop new process technologies within their own R&D organizations and then transfer equipment and processes to chip manufacturers for integration and qualification. That approach becomes increasingly difficult as transistor architecture, materials, wiring, power delivery, memory integration and packaging become interdependent. EPIC is designed to bring those engineering organizations together earlier.

Intel therefore joins a growing ecosystem around the Silicon Valley center. Applied has announced EPIC engagements with major semiconductor manufacturers and technology companies including TSMC, Samsung, Micron, SK hynix, Broadcom and KIOXIA, along with equipment and technology partners including Advantest, SCREEN Semiconductor Solutions and Besi. University participants include Stanford, UC Berkeley, Arizona State University and Rensselaer Polytechnic Institute.

Recent announcements show the breadth of that model. KIOXIA is working with Applied on advanced memory structures, chip stacking and materials engineering. Besi is expanding joint work into hybrid bonding, thermo-compression bonding and new die-on-wafer, die-on-die and die-on-panel architectures. Broadcom is participating around advanced packaging for AI systems.

Intel adds another dimension because the collaboration crosses the semiconductor stack from the transistor through the package. That is increasingly relevant to AI silicon. Performance improvements can no longer depend solely on shrinking transistor dimensions. Leading-edge compute architectures increasingly require simultaneous improvements in transistor structures, metal interconnects, power delivery, thermal management, chiplets, memory interfaces and 2.5D/3D integration.

Intel’s Foveros technology illustrates that transition. By vertically integrating dies, 3D packaging can reduce communication distances and increase interconnect density, but it also creates new challenges around bonding, power distribution, heat removal and manufacturing yield. Addressing those problems earlier in the materials and process-development cycle is precisely the type of problem Applied is positioning EPIC to address.

There is also a strategic geographic element. Applied is placing this collaborative manufacturing R&D capability in Silicon Valley, close to its Santa Clara headquarters and a major concentration of semiconductor design, equipment, AI computing and university research organizations. Intel retains its major process-development operation in Oregon, so the collaboration effectively links two significant U.S. semiconductor R&D centers.

For Applied Materials, EPIC could also provide earlier visibility into the manufacturing requirements of future semiconductor generations. Instead of developing equipment against isolated process requirements, Applied can potentially work with customers and partners on integrated process flows spanning multiple steps. That could become increasingly important as AI pushes semiconductor scaling beyond traditional node shrinks and toward system-level co-optimization.

The Intel announcement should nevertheless be viewed as an R&D collaboration rather than a product announcement. Neither company identified a new Intel process node, processor, accelerator, production date or quantified performance improvement resulting from the partnership. The near-term significance is the expansion of the development infrastructure behind future semiconductor generations — and the emergence of Applied’s Silicon Valley EPIC Center as a shared venue for that work.

Core Business — Semiconductor manufacturing equipment and materials engineering

Technology Areas — Deposition • Etch • Epitaxy • Ion Implant • CMP • Process Control • eBeam Inspection • Advanced Packaging

AI Focus — Leading-edge logic, HBM, chiplets, hybrid bonding, heterogeneous integration and energy-efficient AI compute

EPIC Center — Approximately $5 billion as customer programs scale; Silicon Valley collaborative semiconductor R&D center becoming operationally ready in 2026

Strategic Objective — Shorten the transition from materials and process research to high-volume semiconductor manufacturing through early customer and ecosystem co-development.

June 25, 2026 · SEMICONDUCTORS / ADVANCED PACKAGING Applied Materials Expands DRAM and Advanced Packaging Portfolio Applied introduced manufacturing systems targeting advanced DRAM, HBM, hybrid bonding, TSVs and increasingly complex 3D AI packages.

May 21, 2026 · SEMICONDUCTORS / ADVANCED PACKAGING Broadcom Joins Applied Materials EPIC to Accelerate Chip Packaging Broadcom joined the EPIC ecosystem to collaborate on advanced packaging technologies for next-generation AI systems.

March 11, 2026 · SEMICONDUCTORS / MEMORY Applied Materials, Micron Partner on AI Memory R&D Micron and Applied outlined joint EPIC research spanning advanced DRAM, HBM, NAND and packaging for AI computing.

October 7, 2025 · SEMICONDUCTORS / PROCESS TECHNOLOGY Applied Materials Targets 2nm with Hybrid Bonding, GAA Epi, and eBeam The Kinex, Xtera and PROVision 10 platforms illustrate Applied’s equipment roadmap across hybrid bonding, gate-all-around transistor formation and advanced metrology.

Chips & SupplyUnited States

Networking Startup Eliyan Draws Takeover Interest, Held Early Talks With Arm

Credited to The Information$ · theinformation.com22h ago

Useful

Semiconductor M&A has been humming. One of the next deals could be for Eliyan, whose technology allows separate chips inside an AI system to talk to one another more quickly and efficiently. The five-year-old startup, valued at $1 billion in July, has notified some of its…

View the article · $The Information

Front Method